With the rapid development of mobile devices, internet of things (“IoT”) and system on a chip (“SoC”), the demand for low power for silicon chips has significantly increased. IoT is the internetworking of physical devices, vehicles (a.k.a. “connected devices” and “smart devices”), buildings and other items which are embedded with electronics, software, sensors, actuators, and network connectivity that enable these objects to collect and exchange information. SoC is an integrated circuit (“IC”) that integrates all components of a computer or other electronic system into a single chip. SoC may contain digital, analog, mixed-signal, and radio-frequency functions, all of which reside on a single chip substrate. Due to their low power-consumption, SoCs are widely implemented in mobile electronics and IoT.
Advances in integrated circuit manufacturing processes have enabled SoC designs with ever increasing complexities and functions that consume more power. In order to extend battery life, reduce overall system cost and improve market competitiveness, mobile devices and IoT devices require low-power chip designs.
Such demand for low-power chip-design requires that design tools communicate low-power design parameters in a single, standard format to achieve low-power design efficiency. In the power domain of the low-power design parameters, the power-ground (“PG”) nets and connectivity are determining factors for the chip efficiency. As discussed herein, a cell with power-ground strips is called a PG cell.